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Additional info for ACM Transactions on Design Automation of Electronic Systems (January)
ACM Transactions on Design Automation of Electronic Systems, Vol. 10, No. 1, January 2005. A Scheduling Algorithm for Optimization and Early Planning • 35 Fig. 1. A representative flow for automatic mapping of applications from high-level descriptions to a programmable system. In this work, we present a scheduling algorithm for data flow graphs (DFGs), which is an integral element within the high-level synthesis stage of this automated flow. Our method “simultaneously” assigns a set of operations within the input DFG to control steps.
In addition, bipartition signal/dual-encoding architectures also take the power dissipation of pipeline registers into account by applying a codec structure, which significantly reduces power dissipation. Our accurate transistor-level simulations demonstrate the practical impact of the partition and encoding approaches in lowering the power of pipelined circuits. 1% on average for pipeline registers and total power consumption, respectively, can be obtained by the bipartition dual-encoding architecture.
The input to our algorithm is a data flow graph, and resource constraints for each resource type. In the following we will present details of the two main tasks within our algorithm. 1 Selection of Operation Chains. At each step we extract a chain of operations from the input DFG. We start with extracting the longest path from the DFG. After one set of operations are scheduled those operations are removed from the DFG and the next longest path within the remaining graph is found. In this manner paths are selected in decreasing order of path delays.
ACM Transactions on Design Automation of Electronic Systems (January) by M. Gasteier, S. Liao, X. Song on the crossing distribution problem, J.-Y. Jou on two-level logic minimization for low power, F. Vahid on procedure cloning, Q. Wang, G. Yeap on power reduction and power delay trade-offs, others M. Glesner